1. Field of the Invention
This invention relates in general to a signal detection circuit and, more particularly, to a signal detection circuit the output voltage of which is not affected by minute voltage fluctuations contained in the input signals. The present invention has a particular applicability to a signal detection circuit for input signals encoded in accordance with Alternate Mark Inversion.
2. Description of the Background Art
The integrated services digital network (hereinafter referred to as ISDN) can be regarded as a system for realizing various communications such as telephone, facsimile communication, data communication and image communication in a digitized network. In the conventional communication services before the ISDN, the interface between the terminal equipment of a user and the network is adapted only to a fixed one usage such as an interface for telephone, an interface for data communication, or the like. However, in the ISDN, an integrated interface for the above described various services is defined. The interface is called a multipurpose user network interface which is clearly defined by international telegraph and telephone consultative committee (hereinafter referred to as CCITT).
FIG. 3 is a diagrammatic view showing an example of a portion of the conventional ISDN. Referring to FIG. 3, in ISDN, the ISDN exchanges in a telephone station and the ISDN terminals in the user's premises are interconnected by a telephone network. A network termination unit 100 is provided in the user's premises, and the telephone network and the user's four-wire bus are connected to this termination unit 100. The ISDN terminals are connected via user's four-wire bus to the network termination unit 100. In the network termination unit 100, an interface circuit 101 is provided for connection with the user's four-wire bus.
FIG. 4A is a block diagram showing the interface circuit 101 provided in the network termination unit 100 shown in FIG. 3. Referring to FIG. 4A, the interface circuit 101 includes a driver 52 and a receiver 30 connected to the user's four-wire bus 61 and 62 respectively, frame buffers 51 and 53 connected to the driver 52 and receiver 30, a controller 55 for controlling the frame buffers 51 and 53 respectively and a reference voltage source 56 for supplying reference voltage V.sub.ref to the driver 52 and receiver 30. The digital signals supplied via the frame buffer 51 are converted by the driver into corresponding analog signals. On the other hand, the analog signals supplied via the user's four-wire bus 62 are converted into the digital form by the receiver 30 so as to be then supplied to the frame buffer 53.
In operation, digital data transmitted from a digital signal processing circuit (not shown) provided in the network termination unit 100 through a telephone network are applied to a frame buffer 51. The digital data are applied from the frame buffer 51 to a driver 52 for alternate mark inversion (hereinafter referred to as AMI). The driver 52 transmits the data which are turned into AMI codes to a user's ISDN terminal through a transmission bus line 61 in response to a digital signal. Meanwhile, a receiver 30 receives the AMI codes outputted from the ISDN terminal through a receiving bus 62. The receiver 30 detects digital data transmitted through the ISDN terminal in response to the received AMI codes. The digital data detected by the receiver 30 are applied to the frame buffer 53 and a PLL circuit 54 for error control. The digital data applied to the frame buffer 53 are applied to the digital signal processing circuit to be processed for transmission through the telephone network. The PLL circuit applies a control signal for error control to a controlling portion 55 in response to the digital data. The controlling portion 55 controls the above described operations in the interface circuit 101.
Referring to FIG. 4B, the network termination unit 100 and the ISDN terminals 70 are connected through user's 4-wire bus line 60 formed of a transmission bus 61 and a receiving bus 62. Sockets 73 are used for connecting the terminals 70 and buses 61 and 62. One ISDN terminal 70 comprises a receiver 71 connected to the bus 61 and a driver 72 connected to the bus 62. AMI coded data D1 and D2 of 48 bits for each frame are transmitted through the buses 61 and 62, respectively.
FIG. 5 is a waveform diagram showing examples of input and output signals supplied in the interface circuit shown in FIG. 4A via user's four-wire bus. As shown in FIG. 5, the signals coded by using AMI are transmitted via the user's four-wire bus between the network termination unit 100 and the ISDN terminal. As is apparent from FIG. 5, the binary data "0" is defined by a pulse having positive or negative polarity in the AMI. Meanwhile, the binary data "1" is defined by the absence of the pulse. In addition, the pulse polarity of the data "0" is determined by inverting the polarity of the directly proceeding "0". The DC level of the signals to be transmitted is not necessary when the AMI coding is used, so that alternate data transmission which is immune to the noises can be realized. The usage of the AMI coding is requested by the above mentioned CCITT for the ISDN.
FIG. 6 is a block diagram showing the receiver 30 shown in FIG. 4A. Referring to FIG. 6, the receiver 30 includes a filter section 31 connected for receiving signals from the user's four-wire bus, a peak hold or tracking circuit 32 connected to the output of the filter section 31, a data detector 33 connected to the output of the peak hold circuit 32, and an analog voltage generator 34 connected to receive the reference voltage V.sub.ref from the reference voltage source. The filter section 31 includes a low pass filter and a high pass filter. The peak hold circuit 32 receives the voltage signal Vin freed of noises by the filter section 31 and supplies a voltage corresponding to the peak voltage of the received signal to the data detector 33. The data detector 33 compares the voltage signal from the peak hold circuit 32 with the signal Vin from the filter section 31.
FIG. 7 is a circuit diagram showing an example of the conventional peak hold circuit shown in FIG. 6. The peak hold circuit shown in this figure may be seen for example in the Digest of Technical Papers, pages 108 and 109, in the IEEE International Solid State Circuits Conference held in 1988. It is noted that the example of the driver and receiver circuit shown in FIG. 4A is also reported in this Digest.
Referring to FIG. 7, the peak hold circuit 32 including an operational amplifier 1 having its non-inverting input connected for receiving the input voltage Vin, a MOS transistor 3 and a resistor 7 connected in series between the electrical source 10 and a reference voltage line 24, and a capacitor 5 connected in parallel with the resistor 7. The operational amplifier 1 has its inverting input connected to a common junction between the transistor 3 and the resistor 7. The transistor 3 has its gate connected to the output of the operational amplifier 1. The reference voltage line 24 is connected to the output of an operational amplifier 23 forming a voltage follower. The operational amplifier 23 is connected to an analog ground 19 to hold the reference voltage line 24 at an analog ground voltage Vag. The peak hold circuit 32 further includes an operational amplifier 2 having its non-inverting input connected for receiving the input voltage Vin, a resistor 8 and a PMOS transistor 4 connected in series between the reference voltage line 24 and the ground 11, and a capacitor 6 connected in parallel with the resistor 8. The operational amplifier 2 has its inverting input connected to a common junction between the resistor 8 and the transistor 4. The transistor 4 has its gate connected to the output of the operational amplifier 2.
The data detector 33 includes two comparators 20 and 21. The comparator 20 has its non-inverting input connected for receiving the input voltage Vin and has its inverting input connected for receiving a voltage Vth1 produced by voltage division by the resistor 7. The comparator 21 has its non-inverting input connected for receiving a voltage Vth2 obtained by voltage division by the resistor 8, and has its inverting input connected for receiving the input voltage Vin. The comparators 20 and 21 produce output voltages Vo1 and Vo2 indicating the respective results of comparison.
FIG. 8 is a timing chart for illustrating the operation of the peak hold circuit 32 shown in FIG. 7. The operation of the circuit is hereinafter explained by referring to FIGS. 7 and 8.
When a positive pulse is supplied as the input voltage Vin, transistor 3 is turned on. The capacitor 5 is charged by the voltage from the source potential 10 supplied via transistor 3. As the capacitor 5 is charged, transistor 3 is turned off gradually. Thus, a peak voltage Vpk1 corresponding to the peak value of the input voltage Vin is stored in the capacitor 5. The voltage Vth1 corresponding to the voltage Vpk1 held by the capacitor 5 is outputted after voltage division by the resistor 7. The voltage Vpk1 charged by the capacitor 5 is discharged via resistor 7 and reference voltage line 24. The discharge time constant is determined by the resistance of the resistor 7 and the capacitance of the capacitor 5. In general, the voltage Vpk1 and the output voltage Vth1 reach the analog ground voltage Vag before the next positive pulse is supplied.
On the other hand, when a negative pulse is supplied as the input voltage Vin, the peak voltage Vpk2 is held in the capacitor 6 in the same way as above. Thus the voltage Vth2 corresponding to the peak voltage Vpk2 is outputted via resistor 8.
Generally, the distances between the network termination unit and the each of the ISDN terminals connected through the user's 4-wire bus line are different, so that the voltage level Vin of the input signals of the peak hold circuit 32 changes corresponding to the terminals through which the input signals are transmitted. Consequently, the data detector 33 shown in FIG. 7 cannot detect exactly the transmitted data when a fixed threshold value is used as a reference level. Therefore, the peak hold circuit 32 generates variable threshold voltages Vth1 and Vth2 in response to the input voltage Vin. Referring to FIG. 9, peak voltages Vpk1 and Vpk2 and threshold voltages Vth1 and Vth2 provided based on input voltages Vin having different amplitudes and polarities are shown. The comparators 20 and 21 in the data detector 33 compare the input voltages Vin with the voltages Vth1 and Vth2 outputted from the peak hold circuit 32 as a reference voltages, respectively. Therefore, even if various voltage levels of the input signals are applied, the data detector 33 can exactly detect the transmitted data.
In the conventional peak hold circuit, when minute voltage fluctuations are contained in the input voltage Vin, the following problems are presented. That is, when an input voltage Vin effective as the input signal is not supplied, a back pulse A or noise B as shown in FIG. 8 are occasionally contained in the input signal Vin. The back pulse A is generated by, for example, a mismatch between an impedance of a bus line and an output impedance of a driver circuit in a transmitter of the input signal. In addition, the pulse signals on the bus line often include overshoot and undershoot which are the causes of the back pulse A. In addition, overshoot and the undershoot are sometimes generated in the input circuits provided in a semiconductor chip, for example, in the input buffer, the low pass filter and the like. Meanwhile, the noise B is generated mainly by the capacitive coupling between the interconnection in the semiconductor chip for transmitting the input voltage Vin and other interconnections. In such a case, the conventional peak hold circuit 32 operates responsive to the minute voltage fluctuations contained in the input voltage Vin. Thus the mistaken output voltages Vth1 and Vth2, in other words, the output voltage which should have not been outputted, are outputted by the peak hold circuit 32, so that the data detector 33 also outputs mistaken output voltages Vo1 and Vo2.
Also, when no input voltage Vin is supplied, the voltage Vin and the voltages Vth1 and Vth2 reach the analog ground voltage Vag. Hence, when the comparators 20 and 21 include offset voltages, the comparators 20 and 21 occasionally operate in a mistaken manner. The offset voltage of the comparator is generally generated by the different between the characteristics of the two transistors in the comparator to which two differential input terminals are connected. More specifically, the offset voltage is generated by the different between the threshold voltages of the two transistors and the differences in the voltage amplification rates thereof.